Scaling of CMOS transistor devices to smaller and smaller dimensions to enable larger circuit density is running into challenges wherein the performance of such ultra small devices is not scaling favorably due to short channel effect in the device behavior, the difficulty in scaling channel strain induced mobility enhancements and the like. Additionally, with increased logic circuit density, the demand for memory accessible by logic circuits with minimal delay and memory bandwidth to access a large segment of the memory at a given time, are becoming paramount to achieving peak performance. This in turn drives two requirements. First, additional memory needs to be embedded along with the logic circuitry on the same chip thus competing for the silicon real estate on the chip. Second, fast access and high bandwidth interconnects are required for the logic circuits to send and retrieve information from these memory cells on the chip thus driving a huge increase in interconnect density and speed.
This in turn drives the interconnect needs for future microprocessors and other high performance chips, requiring a continued push to lower effective dielectric constant (referred to hereinafter as kef) of inter-level dielectric materials, higher aspect ratio (wire height over wire width) for all wiring levels, and increasing number of metallization layers. At this point the back-end-of-the-line (BEOL) interconnects may consist of as many as ten metallization levels that contain wires to provide interconnections for signal, clock, power, repeaters, devices, decoupling elements, and the like. As future interconnects shrink in dimension to allow gigascale device integration, the signal delay and the signal fidelity problems associated with the interconnects become significant limiters of the overall system performance. Therefore, it has been realized that there will be a slow down in the rate of performance improvements for new generations relative to the famous Moore's law of microprocessors if one were to depend on the current state of the art planar chip architectures alone. New solutions therefore become a necessity if significant improvements are to be achieved in future IC generations.
To overcome the limitations of the fully planar integration schemes a variety of three-dimensional (3D) integration and packaging techniques are being evaluated in the art. The main considerations behind the use of 3D Integration are: minimization of the interconnect wire length and especially the long interconnects due to the ability to connect vertically between a 3D stack of device layers and the implementation of related design flexibility including new system architectures afforded by stacked device layers. For example, it is possible to stack a memory device layer on a logic device layer and enable a larger amount of memory connected to the logic at a high band width by means of vertical via interconnects.
For 3DI device integration a composite interface joining such as Transfer & Joining (T&J) has demonstrated good success in practice. In this T&J method the metal studs on the bottom surface of the top wafer are mated with a recessed metal pad at the bottom of blind vias located at the top surface of the bottom wafer. The top surface of the bottom wafer is provided with an adhesive to facilitate the dielectric bonding while the metal studs and recessed pads in the blind vias bond to form metal connection. Both connections are formed in a single lamination step. This stud in via arrangement allows an accurate positioning of the two wafers, eliminates slippage and distortion between the two wafers during lamination, and is accommodating to surface topography, among other advantages. The via/stud lock and key combination can be built in reverse order with the studs on the bottom wafer and recessed vias in the top wafer if such a process is called for.
The other joining methods, such as oxide to oxide and Cu to Cu thermo-compression, are constrained by limited flow of the bonded materials and thus require stringent tolerance on the mating surfaces. Further the initial alignment between the mating features has to be maintained through additional mechanical attributes such as special fixtures or tooling. However in the T&J approach, the lock and key aspect of the stud and recessed pad under a via helps partially to assure retention of the initial good alignment.
While forming a metal and dielectric connection in one lamination step has advantages for the T&J connection method, T&J addresses only interface bonding (studs into blind vias) and does not address the issue of through-via connection required for layer to layer connection in a 3D device stack. For this purpose, through-silicon-vias are required and are formed in a different step to enable contacts to be brought to the top surface of the upper device wafer, or bottom of the lower device wafer for controlled collapse chip connections (C4) to the outside world or to a third device layer.
Currently practiced through-via methods in the art include deep silicon etch with W fill (typically about 10 to about 50 um wide and up to about 150 um deep) or moderate depth-via methods are quite elaborate in process and limited in pitch achievable and hence not easily extendible to finer feature high density device-device connection.
At this point, 3D wafer-scale integration is a relatively new technology and further investigations including methodologies for reliable etching, cleaning, filling, aligning, bonding integrity, wafer-scale planarity, and integration with active circuits and the like have to be fully demonstrated. 3D integration based on stacking of wafer-level device layers has been a main focus of 3D IC technology. This process includes fabrication of each component on a separate wafer with its optimized processing technology, followed by aligning, bonding, and vertical interconnection of the wafers to build a new high functionality system.
Some of the key challenges in this regard include: formation and filling of deep vias (about 50 to about 150 micron deep, about 2 to about 50 micron in diameter typically) in silicon and reliably filling the same with metal; the ability to reliably align multiple device layers to each other in a precise fashion, and join to enable vertical electrical connections in adequate numbers at fine pitch; and lastly, achieving good mechanical bonding between the bonded layers and the like. Tooling is available to make deep vias in silicon but reliably filling such vias with metals is a challenge. Available alignment tools can at best achieve about 1 to about 2 micron alignment accuracy which tends to limit the size and pitches of the bonding features which in turn can limit the vertical interconnect density and count. Oxide-oxide bonds and metal-metal bonds typically used do not provide adequate mechanical bond strength between layers especially if the allowed bonding temperatures are restricted to about 40° C. to be compatible with pre-existing on chip interconnects in the device layers being bonded.